\section{Scope and Innovation}
\label{sec:scope}As a first step in the proposed research, we will
perform a comprehensive and thorough analysis, comparing the energy
dissipation and performance of processors based on standard
transistors(FinFETs) and TFETs for a range of $V_{DD}$s, considering
process variations. Physics-based device models will be used to
quantify the impact of process variations on the power and performance
of TFETs and FinFETs. This analysis will provide useful insights into
the circuit and system implications of TFETs and define the design
space where TFETs outperform FinFETs.

The next stage of the project primarily focuses on two levels in the
cross-layer optimization space:
\begin{itemize} \itemsep1pt \parskip0pt \parsep0pt
\item At the circuit-level, we will explore new flip-flop topologies
  and other standard cells suitable for TFETs and perform a thorough
  layout optimization to minimize the area and interconnect parasitic
  capacitance. Exploration of new memory-design techniques is beyond the
  scope of this work, but, in keeping with prior work~\cite{Swaminathan_SystemLevelTFET_ISCA14} we will use the existing TFET memories for
  our investigations at the architectural level.

\item At the architecture-level, we will explore techniques like
  RAZOR~\cite{Razor} and ReCycle~\cite{ReCycle_ISCA07} which will
  increase the robustness of TFET-based processors to process
  variations and lower the design margins. 
\end{itemize} \itemsep1pt \parskip0pt \parsep0pt

New circuit techniques proposed in this research will define the
specifications for the architectural techniques to achieve maximum
increase in the robustness to process variations. In addition, reduced
design margins achieved by the architectural techniques will enable
the optimization of the energy efficiency of TFET-based flip-flops and
other standard cells. Such a unique co-design approach proposed in
this research will enable the operation of TFET-based processors at
significantly higher energy efficiency.

This research project will require close interactions between circuit
and architecture experts due to the multi-dimensional nature of the
problem and the cross-layer optimization approach that we are
proposing as a part of our research thrust. A close collaboration will
be established between Prof. Gupta with an expertise in low power
variation-aware circuit design in exploratory technologies and
Prof. Sampson, who is an expert in the architectural design of
processors based on emerging devices. Penn State is a leader in TFET
research, and both investigators will benefit from local expertise.


% LocalWords:  FinFETs TFETs VDDs topologies ReCycle TFET
